25 citations · 46 across the 7 of their papers we have counts for
7 papers
Accelerating Variational Quantum Algorithms Using Circuit Concurrency
Salonik Resch, Anthony Gutierrez, Joon Suk Huh +5
Variational quantum algorithms (VQAs) provide a promising approach to achieve quantum advantage in the noisy intermediate-scale quantum era. In this era, quantum computers experien…
High-Performance and Energy-Effcient Memory Scheduler Design for Heterogeneous Systems
Rachata Ausavarungnirun, Gabriel H. Loh, Lavanya Subramanian +2
When multiple processor cores (CPUs) and a GPU integrated together on the same chip share the off-chip DRAM, requests from the GPU can heavily interfere with requests from the CPUs…
Holistic Management of the GPGPU Memory Hierarchy to Manage Warp-level Latency Tolerance
Rachata Ausavarungnirun, Saugata Ghose, Onur Kayıran +4
In a modern GPU architecture, all threads within a warp execute the same instruction in lockstep. For a memory instruction, this can lead to memory divergence: the memory requests…
CODA: Enabling Co-location of Computation and Data for Near-Data Processing
Hyojong Kim, Ramyad Hadidi, Lifeng Nai +5
Recent studies have demonstrated that near-data processing (NDP) is an effective technique for improving performance and energy efficiency of data-intensive workloads. However, lev…
GPU System Calls
Ján Veselý, Arkaprava Basu, Abhishek Bhattacharjee +3
GPUs are becoming first-class compute citizens and are being tasked to perform increasingly complex work. Modern GPUs increasingly support programmability- enhancing features such…
Achieving both High Energy Efficiency and High Performance in On-Chip Communication using Hierarchical Rings with Deflection Routing
Rachata Ausavarungnirun, Chris Fallin, Xiangyao Yu +5
Hierarchical ring networks, which hierarchically connect multiple levels of rings, have been proposed in the past to improve the scalability of ring interconnects, but past hierarc…
Enabling Efficient Dynamic Resizing of Large DRAM Caches via A Hardware Consistent Hashing Mechanism
Kevin K. Chang, Gabriel H. Loh, Mithuna Thottethodi +6
Die-stacked DRAM has been proposed for use as a large, high-bandwidth, last-level cache with hundreds or thousands of megabytes of capacity. Not all workloads (or phases) can produ…