39 citations · 167 across the 24 of their papers we have counts for
26 papers
Ariadne: A Hotness-Aware and Size-Adaptive Compressed Swap Technique for Fast Application Relaunch and Reduced CPU Usage on Mobile Devices
Yu Liang, Aofeng Shen, Chun Jason Xue +9
Growing application memory demands and concurrent usage are making mobile device memory scarce. When memory pressure is high, current mobile systems use a RAM-based compressed swap…
Utopia: Fast and Efficient Address Translation via Hybrid Restrictive & Flexible Virtual-to-Physical Address Mappings
Konstantinos Kanellopoulos, Rahul Bera, Kosta Stojiljkovic +8
Conventional virtual memory (VM) frameworks enable a virtual address to flexibly map to any physical address. This flexibility necessitates large data structures to store virtual-t…
RevaMp3D: Architecting the Processor Core and Cache Hierarchy for Systems with Monolithically-Integrated Logic and Memory
Nika Mansouri Ghiasi, Mohammad Sadrosadati, Geraldo F. Oliveira +9
Recent nano-technological advances enable the Monolithic 3D (M3D) integration of multiple memory and logic layers in a single chip, allowing for fine-grained connections between la…
GenStore: A High-Performance and Energy-Efficient In-Storage Computing System for Genome Sequence Analysis
Nika Mansouri Ghiasi, Jisung Park, Harun Mustafa +11
Read mapping is a fundamental, yet computationally-expensive step in many genomics applications. It is used to identify potential matches and differences between fragments (called…
Energy-Efficient Deflection-based On-chip Networks: Topology, Routing, Flow Control
Rachata Ausavarungnirun, Onur Mutlu
As the number of cores scales to tens and hundreds, the energy consumption of routers across various types of on-chip networks in chip muiltiprocessors (CMPs) increases significant…
SISA: Set-Centric Instruction Set Architecture for Graph Mining on Processing-in-Memory Systems
Maciej Besta, Raghavendra Kanakagiri, Grzegorz Kwasniewski +15
Simple graph algorithms such as PageRank have been the target of numerous hardware accelerators. Yet, there also exist much more complex graph mining algorithms for problems such a…
A Modern Primer on Processing in Memory
Onur Mutlu, Saugata Ghose, Juan Gómez-Luna +3
This paper discusses recent research that aims to enable computation close to data, an approach we broadly call processing-in-memory (PIM). PIM places computation mechanisms in or…
Slim NoC: A Low-Diameter On-Chip Network Topology for High Energy Efficiency and Scalability
Maciej Besta, Syed Minhaj Hassan, Sudhakar Yalamanchili +3
Emerging chips with hundreds and thousands of cores require networks with unprecedented energy/area efficiency and scalability. To address this, we propose Slim NoC (SN): a new on-…
Enabling High-Capacity, Latency-Tolerant, and Highly-Concurrent GPU Register Files via Software/Hardware Cooperation
Mohammad Sadrosadati, Amirhossein Mirhosseini, Ali Hajiabadi +7
Graphics Processing Units (GPUs) employ large register files to accommodate all active threads and accelerate context switching. Unfortunately, register files are a scalability bot…
GenASM: A High-Performance, Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis
Damla Senol Cali, Gurpreet S. Kalsi, Zülal Bingöl +13
Genome sequence analysis has enabled significant advancements in medical and scientific areas such as personalized medicine, outbreak tracing, and the understanding of evolution. U…
The Virtual Block Interface: A Flexible Alternative to the Conventional Virtual Memory Framework
Nastaran Hajinazar, Pratyush Patel, Minesh Patel +7
Computers continue to diversify with respect to system designs, emerging memory technologies, and application memory demands. Unfortunately, continually adapting the conventional v…
NOM: Network-On-Memory for Inter-Bank Data Transfer in Highly-Banked Memories
Seyyed Hossein SeyyedAghaei Rezaei, Mehdi Modarressi, Rachata Ausavarungnirun +3
Data copy is a widely-used memory operation in many programs and operating system services. In conventional computers, data copy is often carried out by two separate read and write…
Enabling Practical Processing in and near Memory for Data-Intensive Computing
Onur Mutlu, Saugata Ghose, Juan Gómez-Luna +1
Modern computing systems suffer from the dichotomy between computation on one side, which is performed only in the processor (and accelerators), and data storage/movement on the ot…
Processing Data Where It Makes Sense: Enabling In-Memory Computation
Onur Mutlu, Saugata Ghose, Juan Gómez-Luna +1
Today's systems are overwhelmingly designed to move data to computation. This design choice goes directly against at least three key trends in systems that cause performance, scala…
Techniques for Efficiently Handling Power Surges in Fuel Cell Powered Data Centers: Modeling, Analysis, Results
Yang Li, Di Wang, Saugata Ghose +7
Fuel cells are a promising power source for future data centers, offering high energy efficiency, low greenhouse gas emissions, and high reliability. However, due to mechanical lim…
RowClone: Accelerating Data Movement and Initialization Using DRAM
Vivek Seshadri, Yoongu Kim, Chris Fallin +8
In existing systems, to perform any bulk data movement operation (copy or initialization), the data has to first be read into the on-chip processor, all the way into the L1 cache,…
Mosaic: An Application-Transparent Hardware-Software Cooperative Memory Manager for GPUs
Rachata Ausavarungnirun, Joshua Landgraf, Vance Miller +4
Modern GPUs face a trade-off on how the page size used for memory management affects address translation and demand paging. Support for multiple page sizes can help relax the page…
High-Performance and Energy-Effcient Memory Scheduler Design for Heterogeneous Systems
Rachata Ausavarungnirun, Gabriel H. Loh, Lavanya Subramanian +2
When multiple processor cores (CPUs) and a GPU integrated together on the same chip share the off-chip DRAM, requests from the GPU can heavily interfere with requests from the CPUs…
A Memory Controller with Row Buffer Locality Awareness for Hybrid Memory Systems
HanBin Yoon, Justin Meza, Rachata Ausavarungnirun +2
Non-volatile memory (NVM) is a class of promising scalable memory technologies that can potentially offer higher capacity than DRAM at the same cost point. Unfortunately, the acces…
Holistic Management of the GPGPU Memory Hierarchy to Manage Warp-level Latency Tolerance
Rachata Ausavarungnirun, Saugata Ghose, Onur Kayıran +4
In a modern GPU architecture, all threads within a warp execute the same instruction in lockstep. For a memory instruction, this can lead to memory divergence: the memory requests…
Techniques for Shared Resource Management in Systems with Throughput Processors
Rachata Ausavarungnirun
The continued growth of the computational capability of throughput processors has made throughput processors the platform of choice for a wide variety of high performance computing…
Enabling the Adoption of Processing-in-Memory: Challenges, Mechanisms, Future Research Directions
Saugata Ghose, Kevin Hsieh, Amirali Boroumand +2
Poor DRAM technology scaling over the course of many years has caused DRAM-based main memory to increasingly become a larger system bottleneck. A major reason for the bottleneck is…
Improving Multi-Application Concurrency Support Within the GPU Memory System
Rachata Ausavarungnirun, Christopher J. Rossbach, Vance Miller +5
GPUs exploit a high degree of thread-level parallelism to hide long-latency stalls. Due to the heterogeneous compute requirements of different applications, there is a growing need…
Understanding and Exploiting Design-Induced Latency Variation in Modern DRAM Chips
Donghyuk Lee, Samira Khan, Lavanya Subramanian +5
Variation has been shown to exist across the cells within a modern DRAM chip. We empirically demonstrate a new form of variation that exists within a real DRAM chip, induced by the…