18 citations · 19 across the 4 of their papers we have counts for
6 papers · 1 filter
CHARGE: Leveraging CWE Hierarchies for Hardware Security SystemVerilog Assertion Generation
Xiao Tan, Cynthia Sturton
This paper presents CHARGE, an automated framework for generating security properties for unverified RTL modules using CWEs and large language models (LLMs). The hallmark is a reas…
Security Properties for Open-Source Hardware Designs
Jayden Rogers, Niyaz Shakeel, Divya Mankani +4
The hardware security community relies on databases of known vulnerabilities and open-source designs to develop formal verification methods for identifying hardware security flaws.…
Augmented Symbolic Execution for Information Flow in Hardware Designs
Kaki Ryan, Matthew Gregoire, Cynthia Sturton
We present SEIF, a methodology that combines static analysis with symbolic execution to verify and explicate information flow paths in a hardware design. SEIF begins with a statica…
Countering the Path Explosion Problem in the Symbolic Execution of Hardware Designs
Kaki Ryan, Cynthia Sturton
Symbolic execution is a powerful verification tool for hardware designs, but suffers from the path explosion problem. We introduce a new approach, piecewise composition, which leve…
Isadora: Automated Information Flow Property Generation for Hardware Designs
Calvin Deutschbein, Andres Meza, Francesco Restuccia +2
Isadora is a methodology for creating information flow specifications of hardware designs. The methodology combines information flow tracking and specification mining to produce a…
Server-side verification of client behavior in cryptographic protocols
Andrew Chi, Robert Cochran, Marie Nesfield +2
Numerous exploits of client-server protocols and applications involve modifying clients to behave in ways that untampered clients would not, such as crafting malicious packets. In…