3 papers
cs.PF2025
The Configuration Wall: Characterization and Elimination of Accelerator Configuration Overhead
Josse Van Delm, Anton Lydike, Joren Dumoulin +6
Contemporary compute platforms increasingly offload compute kernels from CPU to integrated hardware accelerators to reach maximum performance per Watt. Unfortunately, the time the…
cs.PL2025
A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions
Alexandre Lopoukhine, Federico Ficarelli, Christos Vasiladiotis +6
High-performance micro-kernels must fully exploit today's diverse and specialized hardware to deliver peak performance to DNNs. While higher-level optimizations for DNNs are offere…
cs.DC2024
MATCH: Model-Aware TVM-based Compilation for Heterogeneous Edge Devices
Mohamed Amine Hamdi, Francesco Daghero, Giuseppe Maria Sarda +6
Streamlining the deployment of Deep Neural Networks (DNNs) on heterogeneous edge platforms, coupling within the same micro-controller unit (MCU) instruction processors and hardware…