13 citations · 32 across the 18 of their papers we have counts for
4 papers · 1 filter
DCSYNTH: Guided Reactive Synthesis with Soft Requirements for Robust Controller and Shield Synthesis
Amol Wakankar, Paritosh K. Pandya, Raj Mohan Matteplackel
DCSYNTH is a tool for the synthesis of controllers from safety and bounded liveness requirements given in interval temporal logic QDDC. It investigates the role of soft requirement…
Formalizing Timing Diagram Requirements in Discrete Duration Calulus
Raj Mohan Matteplackel, Paritosh K. Pandya, Amol Wakankar
Several temporal logics have been proposed to formalise timing diagram requirements over hardware and embedded controllers. These include LTL, discrete time MTL and the recent indu…
Making Metric Temporal Logic Rational
Shankara Narayanan Krishna, Khushraj Madnani, P. K. Pandya
We study an extension of $\mtl$ in pointwise time with rational expression guarded modality $\reg_I(\re)$ where $\re$ is a rational expression over subformulae. We study the decida…
Deterministic Temporal Logics and Interval Constraints
Kamal Lodaya, Paritosh K. Pandya
In temporal logics, a central question is about the choice of modalities and their relative expressive power, in comparison to the complexity of decision problems such as satisfiab…