3 citations · 7 across the 4 of their papers we have counts for
9 papers
Generalizing Non-Punctuality for Timed Temporal Logic with Freeze Quantifiers
Shankara Narayanan Krishna, Khushraj Madnani, Manuel Mazo +1
Metric Temporal Logic (MTL) and Timed Propositional Temporal Logic (TPTL) are prominent real-time extensions of Linear Temporal Logic (LTL). In general, the satisfiability checking…
Specification and Optimal Reactive Synthesis of Run-time Enforcement Shields
Paritosh K. Pandya, Amol Wakankar
A system with sporadic errors (SSE) is a controller which produces high quality output but it may occasionally violate a critical requirement REQ(I,O). A run-time enforcement shiel…
Specification and Reactive Synthesis of Robust Controllers
Paritosh K. Pandya, Amol Wakankar
This paper investigates the synthesis of robust controllers from logical specification of regular properties given in an interval temporal logic QDDC. Our specification encompasses…
DCSYNTH: Guided Reactive Synthesis with Soft Requirements
Amol Wakankar, Paritosh K. Pandya, Rajmohan Matteplackel
In reactive controller synthesis, a number of implementations (controllers) are possible for a given specification because of the incomplete nature of specification. To choose the…
Büchi-Kamp Theorems for 1-clock ATA
Shankara Narayanan Krishna, Khushraj Madnani, Paritosh Pandya
This paper investigates Kamp-like and Büchi-like theorems for 1-clock Alternating Timed Automata (1-ATA) and its natural subclasses. A notion of 1-ATA with loop-free-resets is defi…
DCSYNTH: Guided Reactive Synthesis with Soft Requirements for Robust Controller and Shield Synthesis
Amol Wakankar, Paritosh K. Pandya, Raj Mohan Matteplackel
DCSYNTH is a tool for the synthesis of controllers from safety and bounded liveness requirements given in interval temporal logic QDDC. It investigates the role of soft requirement…