64 citations · 81 across the 8 of their papers we have counts for
5 papers · 1 filter
Slim NoC: A Low-Diameter On-Chip Network Topology for High Energy Efficiency and Scalability
Maciej Besta, Syed Minhaj Hassan, Sudhakar Yalamanchili +3
Emerging chips with hundreds and thousands of cores require networks with unprecedented energy/area efficiency and scalability. To address this, we propose Slim NoC (SN): a new on-…
TRINITY: Coordinated Performance, Energy and Temperature Management in 3D Processor-Memory Stacks
Karthik Rao, William Song, Yorai Wardi +1
The consistent demand for better performance has lead to innovations at hardware and microarchitectural levels. 3D stacking of memory and logic dies delivers an order of magnitude…
Memory Slices: A Modular Building Block for Scalable, Intelligent Memory Systems
Bahar Asgari, Saibal Mukhopadhyay, Sudhakar Yalamanchili
While reduction in feature size makes computation cheaper in terms of latency, area, and power consumption, performance of emerging data-intensive applications is determined by dat…
NeuroTrainer: An Intelligent Memory Module for Deep Learning Training
Duckhwan Kim, Taesik Na, Sudhakar Yalamanchili +1
This paper presents, NeuroTrainer, an intelligent memory module with in-memory accelerators that forms the building block of a scalable architecture for energy efficient training f…
Demystifying the Characteristics of 3D-Stacked Memories: A Case Study for Hybrid Memory Cube
Ramyad Hadidi, Bahar Asgari, Burhan Ahmad Mudassar +3
Three-dimensional (3D)-stacking technology, which enables the integration of DRAM and logic dies, offers high bandwidth and low energy consumption. This technology also empowers ne…