activity
20152020
most citedDemystifying the Characteristics of 3D-Stacked Memories: A Case Study for Hybrid Memory Cube

64 citations · 81 across the 8 of their papers we have counts for

collaborators

9 papers

cs.AR2020★ 5 cited

Slim NoC: A Low-Diameter On-Chip Network Topology for High Energy Efficiency and Scalability

Maciej Besta, Syed Minhaj Hassan, Sudhakar Yalamanchili +3

Emerging chips with hundreds and thousands of cores require networks with unprecedented energy/area efficiency and scalability. To address this, we propose Slim NoC (SN): a new on-…

cs.AR2018

TRINITY: Coordinated Performance, Energy and Temperature Management in 3D Processor-Memory Stacks

Karthik Rao, William Song, Yorai Wardi +1

The consistent demand for better performance has lead to innovations at hardware and microarchitectural levels. 3D stacking of memory and logic dies delivers an order of magnitude…

cs.AR2018★ 1 cited

Memory Slices: A Modular Building Block for Scalable, Intelligent Memory Systems

Bahar Asgari, Saibal Mukhopadhyay, Sudhakar Yalamanchili

While reduction in feature size makes computation cheaper in terms of latency, area, and power consumption, performance of emerging data-intensive applications is determined by dat…

cs.AR2017★ 1 cited

NeuroTrainer: An Intelligent Memory Module for Deep Learning Training

Duckhwan Kim, Taesik Na, Sudhakar Yalamanchili +1

This paper presents, NeuroTrainer, an intelligent memory module with in-memory accelerators that forms the building block of a scalable architecture for energy efficient training f…

cs.DC2017★ 1 cited

Power Regulation in High Performance Multicore Processors

X. Chen, Y. Wardi, S. Yalamanchili

This paper presents, implements, and evaluates a power-regulation technique for multicore processors, based on an integral controller with adjustable gain. The gain is designed for…

cs.AR2017★ 64 cited

Demystifying the Characteristics of 3D-Stacked Memories: A Case Study for Hybrid Memory Cube

Ramyad Hadidi, Bahar Asgari, Burhan Ahmad Mudassar +3

Three-dimensional (3D)-stacking technology, which enables the integration of DRAM and logic dies, offers high bandwidth and low energy consumption. This technology also empowers ne…

math.OC2016★ 3 cited

IPA in the Loop: Control Design for Throughput Regulation in Computer Processors

Xinwei Chen, Yorai Wardi, Sudhakar Yalamanchili

A new technique for performance regulation in event-driven systems, recently proposed by the authors, consists of an adaptive-gain integral control. The gain is adjusted in the con…

math.OC2016

Performance Regulation of Event-Driven Dynamical Systems Using Infinitesimal Perturbation Analysis

Yorai Wardi, Carla Seatzu, Xinwei Chen +1

This paper presents a performance-regulation method for a class of stochastic timed event-driven systems aimed at output tracking of a given reference setpoint. The systems are eit…

math.OC2015★ 6 cited

Temperature Regulation in Multicore Processors Using Adjustable-Gain Integral Controllers

Karthik Rao, William Song, Sudhakar Yalamanchili +1

This paper considers the problem of temperature regulation in multicore processors by dynamic voltage-frequency scaling. We propose a feedback law that is based on an integral cont…