1 citations · 2 across the 2 of their papers we have counts for
5 papers
Slim NoC: A Low-Diameter On-Chip Network Topology for High Energy Efficiency and Scalability
Maciej Besta, Syed Minhaj Hassan, Sudhakar Yalamanchili +3
Emerging chips with hundreds and thousands of cores require networks with unprecedented energy/area efficiency and scalability. To address this, we propose Slim NoC (SN): a new on-…
Memory Slices: A Modular Building Block for Scalable, Intelligent Memory Systems
Bahar Asgari, Saibal Mukhopadhyay, Sudhakar Yalamanchili
While reduction in feature size makes computation cheaper in terms of latency, area, and power consumption, performance of emerging data-intensive applications is determined by dat…
NeuroTrainer: An Intelligent Memory Module for Deep Learning Training
Duckhwan Kim, Taesik Na, Sudhakar Yalamanchili +1
This paper presents, NeuroTrainer, an intelligent memory module with in-memory accelerators that forms the building block of a scalable architecture for energy efficient training f…
Power Regulation in High Performance Multicore Processors
X. Chen, Y. Wardi, S. Yalamanchili
This paper presents, implements, and evaluates a power-regulation technique for multicore processors, based on an integral controller with adjustable gain. The gain is designed for…
IPA in the Loop: Control Design for Throughput Regulation in Computer Processors
Xinwei Chen, Yorai Wardi, Sudhakar Yalamanchili
A new technique for performance regulation in event-driven systems, recently proposed by the authors, consists of an adaptive-gain integral control. The gain is adjusted in the con…