17 citations · 45 across the 12 of their papers we have counts for
12 papers
Fast Bipartitioned Hybrid Adder Utilizing Carry Select and Carry Lookahead Logic
Padmanabhan Balasubramanian, Douglas L. Maskell
We present a novel fast bipartitioned hybrid adder (FBHA) that utilizes carry-select and carry-lookahead logic. The proposed FBHA is an accurate adder with a significant part and a…
Fault-Tolerant Design Approach Based on Approximate Computing
P Balasubramanian, D L Maskell
Triple Modular Redundancy (TMR) has been traditionally used to ensure complete tolerance to a single fault or a faulty processing unit, where the processing unit may be a circuit o…
Area Optimized Quasi Delay Insensitive Majority Voter for TMR Applications
P Balasubramanian, D L Maskell, N E Mastorakis
Mission-critical and safety-critical applications generally tend to incorporate triple modular redundancy (TMR) to embed fault tolerance in their physical implementations. In a TMR…
Indicating Asynchronous Multipliers
P Balasubramanian, D L Maskell, N E Mastorakis
Multiplication is a basic arithmetic operation that is encountered in almost all general-purpose microprocessing and digital signal processing applications, and multiplication is p…
Indicating Asynchronous Array Multipliers
P Balasubramanian, D L Maskell
Multiplication is an important arithmetic operation that is frequently encountered in microprocessing and digital signal processing applications, and multiplication is physically r…
Asynchronous Early Output Block Carry Lookahead Adder with Improved Quality of Results
P Balasubramanian, D L Maskell, N E Mastorakis
A new asynchronous early output block carry lookahead adder (BCLA) incorporating redundant carries is proposed. Compared to the best of existing semi-custom asynchronous carry look…
Approximate Ripple Carry and Carry Lookahead Adders - A Comparative Analysis
P Balasubramanian, C Dang, D L Maskell +1
Approximate ripple carry adders (RCAs) and carry lookahead adders (CLAs) are presented which are compared with accurate RCAs and CLAs for performing a 32-bit addition. The accurate…
Mathematical Estimation of Logical Masking Capability of Majority/Minority Gates Used in Nanoelectronic Circuits
P Balasubramanian, R T Naayagi
In nanoelectronic circuit synthesis, the majority gate and the inverter form the basic combinational logic primitives. This paper deduces the mathematical formulae to estimate the…
Redundant Logic Insertion and Fault Tolerance Improvement in Combinational Circuits
P Balasubramanian, R T Naayagi
This paper presents a novel method to identify and insert redundant logic into a combinational circuit to improve its fault tolerance without having to replicate the entire circuit…
Asynchronous Early Output Dual-Bit Full Adders Based on Homogeneous and Heterogeneous Delay-Insensitive Data Encoding
P Balasubramanian, K Prasad
This paper presents the designs of asynchronous early output dual-bit full adders without and with redundant logic (implicit) corresponding to homogeneous and heterogeneous delay-i…
Early Output Hybrid Input Encoded Asynchronous Full Adder and Relative-Timed Ripple Carry Adder
P Balasubramanian, K Prasad
This paper presents a new early output hybrid input encoded asynchronous full adder designed using dual-rail and 1-of-4 delay-insensitive data codes. The proposed full adder when c…
Area/latency optimized early output asynchronous full adders and relative-timed ripple carry adders
P Balasubramanian, S Yamashita
This article presents two area/latency optimized gate level asynchronous full adder designs which correspond to early output logic. The proposed full adders are constructed using t…