483 citations · 3k across the 177 of their papers we have counts for
13 papers · 1 filter
Fast Graph Vector Search via Hardware Acceleration and Delayed-Synchronization Traversal
Wenqi Jiang, Hang Hu, Torsten Hoefler +1
Vector search systems are indispensable in large language model (LLM) serving, search engines, and recommender systems, where minimizing online search latency is essential. Among v…
LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems through Polling-Free and Retry-Free Operation
Samuel Riedel, Marc Gantenbein, Alessandro Ottaviano +2
Extensive polling in shared-memory manycore systems can lead to contention, decreased throughput, and poor energy efficiency. Both lock implementations and the general-purpose atom…
RapidChiplet: A Toolchain for Rapid Design Space Exploration of Chiplet Architectures
Patrick Iff, Benigna Bruggmann, Blaise Morel +3
Chiplet architectures are on the rise as they promise to overcome the scaling challenges of monolithic chips. A key component of such architectures is an efficient inter-chiplet in…
Sparse Stream Semantic Registers: A Lightweight ISA Extension Accelerating General Sparse Linear Algebra
Paul Scheffler, Florian Zaruba, Fabian Schuiki +2
Sparse linear algebra is crucial in many application domains, but challenging to handle efficiently in both software and hardware, with one- and two-sided operand sparsity handled…
A High-performance, Energy-efficient Modular DMA Engine Architecture
Thomas Benz, Michael Rogenmoser, Paul Scheffler +5
Data transfers are essential in today's computing systems as latency and complex memory access patterns are increasingly challenging to manage. Direct memory access engines (DMAEs)…
HexaMesh: Scaling to Hundreds of Chiplets with an Optimized Chiplet Arrangement
Patrick Iff, Maciej Besta, Matheus Cavalcante +3
2.5D integration is an important technique to tackle the growing cost of manufacturing chips in advanced technology nodes. This poses the challenge of providing high-performance in…
Sparse Hamming Graph: A Customizable Network-on-Chip Topology
Patrick Iff, Maciej Besta, Matheus Cavalcante +3
Chips with hundreds to thousands of cores require scalable networks-on-chip (NoCs). Customization of the NoC topology is necessary to reach the diverse design goals of different ch…
SISA: Set-Centric Instruction Set Architecture for Graph Mining on Processing-in-Memory Systems
Maciej Besta, Raghavendra Kanakagiri, Grzegorz Kwasniewski +15
Simple graph algorithms such as PageRank have been the target of numerous hardware accelerators. Yet, there also exist much more complex graph mining algorithms for problems such a…
Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra
Paul Scheffler, Florian Zaruba, Fabian Schuiki +2
Sparse-dense linear algebra is crucial in many domains, but challenging to handle efficiently on CPUs, GPUs, and accelerators alike; multiplications with sparse formats like CSR an…
Slim NoC: A Low-Diameter On-Chip Network Topology for High Energy Efficiency and Scalability
Maciej Besta, Syed Minhaj Hassan, Sudhakar Yalamanchili +3
Emerging chips with hundreds and thousands of cores require networks with unprecedented energy/area efficiency and scalability. To address this, we propose Slim NoC (SN): a new on-…
Snitch: A tiny Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads
Florian Zaruba, Fabian Schuiki, Torsten Hoefler +1
Data-parallel applications, such as data analytics, machine learning, and scientific computing, are placing an ever-growing demand on floating-point operations per second on emergi…
Stream Semantic Registers: A Lightweight RISC-V ISA Extension Achieving Full Compute Utilization in Single-Issue Cores
Fabian Schuiki, Florian Zaruba, Torsten Hoefler +1
Single-issue processor cores are very energy efficient but suffer from the von Neumann bottleneck, in that they must explicitly fetch and issue the loads/storse necessary to feed t…
hlslib: Software Engineering for Hardware Design
Johannes de Fine Licht, Torsten Hoefler
High-level synthesis (HLS) tools have brought FPGA development into the mainstream, by allowing programmers to design architectures using familiar languages such as C, C++, and Ope…