54 citations · 112 across the 10 of their papers we have counts for
10 papers
An Energy-Efficient Reconfigurable DTLS Cryptographic Engine for End-to-End Security in IoT Applications
Utsav Banerjee, Chiraag Juvekar, Andrew Wright +2
This paper presents a reconfigurable cryptographic engine that implements the DTLS protocol to enable end-to-end security for IoT. This implementation of the DTLS engine demonstrat…
MI6: Secure Enclaves in a Speculative Out-of-Order Processor
Thomas Bourgeat, Ilia Lebedev, Andrew Wright +3
Recent attacks have broken process isolation by exploiting microarchitectural side channels that allow indirect access to shared microarchitectural state. Enclaves strengthen the p…
Constructing a Weak Memory Model
Sizhuo Zhang, Muralidaran Vijayaraghavan, Andrew Wright +2
Weak memory models are a consequence of the desire on part of architects to preserve all the uniprocessor optimizations while building a shared memory multiprocessor. The efforts t…
BigSparse: High-performance external graph analytics
Sang-Woo Jun, Andy Wright, Sizhuo Zhang +2
We present BigSparse, a fully external graph analytics system that picks up where semi-external systems like FlashGraph and X-Stream, which only store vertex data in memory, left o…
Weak Memory Models with Matching Axiomatic and Operational Definitions
Sizhuo Zhang, Muralidaran Vijayaraghavan, Dan Lustig +1
Memory consistency models are notorious for being difficult to define precisely, to reason about, and to verify. More than a decade of effort has gone into nailing down the definit…
Weak Memory Models: Balancing Definitional Simplicity and Implementation Flexibility
Sizhuo Zhang, Muralidaran Vijayaraghavan, Arvind
The memory model for RISC-V, a newly developed open source ISA, has not been finalized yet and thus, offers an opportunity to evaluate existing memory models. We believe RISC-V sho…