77 citations · 120 across the 7 of their papers we have counts for
7 papers
Honeycomb: ordered key-value store acceleration on an FPGA-based SmartNIC
Junyi Liu, Aleksandar Dragojevic, Shane Flemming +6
In-memory ordered key-value stores are an important building block in modern distributed applications. We present Honeycomb, a hybrid software-hardware system for accelerating read…
Convolution Based Spectral Partitioning Architecture for Hyperspectral Image Classification
Ringo S. W. Chu, Ho-Cheung Ng, Xiwei Wang +1
Hyperspectral images (HSIs) can distinguish materials with high number of spectral bands, which is widely adopted in remote sensing applications and benefits in high accuracy land…
Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going
Erwei Wang, James J. Davis, Ruizhe Zhao +5
Deep neural networks have proven to be particularly effective in visual and audio recognition tasks. Existing models tend to be computationally expensive and memory intensive, howe…
Towards Efficient Convolutional Neural Network for Domain-Specific Applications on FPGA
Ruizhe Zhao, Ho-Cheung Ng, Wayne Luk +1
FPGA becomes a popular technology for implementing Convolutional Neural Network (CNN) in recent years. Most CNN applications on FPGA are domain-specific, e.g., detecting objects fr…
All-passive pixel super-resolution of time-stretch imaging
Antony C. S. Chan, Ho-Cheung Ng, Sharat C. V. Bogaraju +3
Based on image encoding in a serial-temporal format, optical time-stretch imaging entails a stringent requirement of state-of-the- art fast data acquisition unit in order to preser…
A Soft Processor Overlay with Tightly-coupled FPGA Accelerator
Ho-Cheung Ng, Cheng Liu, Hayden Kwok-Hay So
FPGA overlays are commonly implemented as coarse-grained reconfigurable architectures with a goal to improve designers' productivity through balancing flexibility and ease of confi…
Automatic Nested Loop Acceleration on FPGAs Using Soft CGRA Overlay
Cheng Liu, Ho-Cheung Ng, Hayden Kwok-Hay So
Offloading compute intensive nested loops to execute on FPGA accelerators have been demonstrated by numerous researchers as an effective performance enhancement technique across nu…