activity
20152024
most citedThe GAP Benchmark Suite

162 citations · 332 across the 14 of their papers we have counts for

collaborators

14 papers

cs.AR2024

Instruction Scheduling in the Saturn Vector Unit

Jerry Zhao, Daniel Grubb, Miles Rusch +4

While the challenges and solutions for efficient execution of scalable vector ISAs on long-vector-length microarchitectures have been well established, not all of these solutions a…

cs.DC2023★ 36 cited

MoCA: Memory-Centric, Adaptive Execution for Multi-Tenant Deep Neural Networks

Seah Kim, Hasan Genc, Vadim Vadimovich Nikiforov +3

Driven by the wide adoption of deep neural networks (DNNs) across different application domains, multi-tenancy execution, where multiple DNNs are deployed simultaneously on the sam…

cs.CR2022★ 6 cited

Verifying RISC-V Physical Memory Protection

Kevin Cheang, Cameron Rasmussen, Dayeol Lee +3

We formally verify an open-source hardware implementation of physical memory protection (PMP) in RISC-V, which is a standard feature used for memory isolation in security critical…

cs.DC2020★ 29 cited

AutoPhase: Juggling HLS Phase Orderings in Random Forests with Deep Reinforcement Learning

Qijing Huang, Ameer Haj-Ali, William Moses +4

The performance of the code a compiler generates depends on the order in which it applies the optimization passes. Choosing a good order--often referred to as the phase-ordering pr…

cs.DC2019★ 4 cited

Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration

Hasan Genc, Seah Kim, Alon Amid +16

DNN accelerators are often developed and evaluated in isolation without considering the cross-stack, system-level effects in real-world environments. This makes it difficult to app…

cs.LG2019★ 18 cited

A View on Deep Reinforcement Learning in System Optimization

Ameer Haj-Ali, Nesreen K. Ahmed, Ted Willke +3

Many real-world systems problems require reasoning about the long term consequences of actions taken to configure and manage the system. These problems with delayed and often seque…

cs.DC2019★ 2 cited

NeuroVectorizer: End-to-End Vectorization with Deep Reinforcement Learning

Ameer Haj-Ali, Nesreen K. Ahmed, Ted Willke +3

One of the key challenges arising when compilers vectorize loops for today's SIMD-compatible architectures is to decide if vectorization or interleaving is beneficial. Then, the co…

cs.CR2019★ 25 cited

Keystone: An Open Framework for Architecting TEEs

Dayeol Lee, David Kohlbrenner, Shweta Shinde +2

Trusted execution environments (TEEs) are being used in all the devices from embedded sensors to cloud servers and encompass a range of cost, power constraints, and security threat…

cs.PL2019★ 4 cited

AutoPhase: Compiler Phase-Ordering for High Level Synthesis with Deep Reinforcement Learning

Ameer Haj-Ali, Qijing Huang, William Moses +4

The performance of the code generated by a compiler depends on the order in which the optimization passes are applied. In high-level synthesis, the quality of the generated circuit…

cs.CR2018★ 2 cited

Sanctorum: A lightweight security monitor for secure enclaves

Ilia Lebedev, Kyle Hogan, Jules Drean +5

Enclaves have emerged as a particularly compelling primitive to implement trusted execution environments: strongly isolated sensitive user-mode processes in a largely untrusted sof…

cs.DC2018★ 7 cited

Co-Design of Deep Neural Nets and Neural Net Accelerators for Embedded Vision Applications

Kiseok Kwon, Alon Amid, Amir Gholami +3

Deep Learning is arguably the most rapidly evolving research area in recent years. As a result it is not surprising that the design of state-of-the-art deep neural net models proce…

cs.DC2017★ 22 cited

Distributed-Memory Breadth-First Search on Massive Graphs

Aydin Buluc, Scott Beamer, Kamesh Madduri +2

This chapter studies the problem of traversing large graphs using the breadth-first search order on distributed-memory supercomputers. We consider both the traditional level-synchr…

cs.AR2016★ 15 cited

The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V

Christopher Celio, Palmer Dabbelt, David A. Patterson +1

This report makes the case that a well-designed Reduced Instruction Set Computer (RISC) can match, and even exceed, the performance and code density of existing commercial Complex…

cs.DC2015★ 162 cited

The GAP Benchmark Suite

Scott Beamer, Krste Asanović, David Patterson

We present a graph processing benchmark suite with the goal of helping to standardize graph processing evaluations. Fewer differences between graph processing evaluations will make…