182 citations · 726 across the 43 of their papers we have counts for
13 papers · 1 filter
Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting (JM3 Special Session)
Bei Yu, Subhendu Roy, Jhih-Rong Gao +1
Triple patterning lithography (TPL) is one of the most promising techniques in the 14nm logic node and beyond. Conventional LELELE type TPL technology suffers from native conflict…
Layout Decomposition for Quadruple Patterning Lithography and Beyond
Bei Yu, David Z. Pan
For next-generation technology nodes, multiple patterning lithography (MPL) has emerged as a key solution, e.g., triple patterning lithography (TPL) for 14/11nm, and quadruple patt…
Lithography Hotspot Detection and Mitigation in Nanometer VLSI
Jhih-Rong Gao, Bei Yu, David Z. Pan
With continued feature size scaling, even state of the art semiconductor manufacturing processes will often run into layouts with poor printability and yield. Identifying lithograp…
TRIAD: a triple patterning lithography aware detailed router
Yen-Hung Lin, Bei Yu, David Z. Pan +1
TPL-friendly detailed routers require a systematic approach to detect TPL conflicts. However, the complexity of conflict graph (CG) impedes directly detecting TPL conflicts in CG.…
EPIC: Efficient prediction of IC manufacturing hotspots with a unified meta-classification formulation
Duo Ding, Bei Yu, Joydeep Ghosh +1
In this paper we present EPIC, an efficient and effective predictor for IC manufacturing hotspots in deep sub-wavelength lithography. EPIC proposes a unified framework to combine d…
GLOW: A global router for low-power thermal-reliable interconnect synthesis using photonic wavelength multiplexing
Duo Ding, Bei Yu, David Z. Pan
In this paper, we examine the integration potential and explore the design space of low power thermal reliable on-chip interconnect synthesis featuring nanophotonics Wavelength Div…