182 citations · 726 across the 43 of their papers we have counts for
11 papers · 2 filters
Lithography Hotspot Detection and Mitigation in Nanometer VLSI
Jhih-Rong Gao, Bei Yu, David Z. Pan
With continued feature size scaling, even state of the art semiconductor manufacturing processes will often run into layouts with poor printability and yield. Identifying lithograp…
TRIAD: a triple patterning lithography aware detailed router
Yen-Hung Lin, Bei Yu, David Z. Pan +1
TPL-friendly detailed routers require a systematic approach to detect TPL conflicts. However, the complexity of conflict graph (CG) impedes directly detecting TPL conflicts in CG.…
EPIC: Efficient prediction of IC manufacturing hotspots with a unified meta-classification formulation
Duo Ding, Bei Yu, Joydeep Ghosh +1
In this paper we present EPIC, an efficient and effective predictor for IC manufacturing hotspots in deep sub-wavelength lithography. EPIC proposes a unified framework to combine d…
GLOW: A global router for low-power thermal-reliable interconnect synthesis using photonic wavelength multiplexing
Duo Ding, Bei Yu, David Z. Pan
In this paper, we examine the integration potential and explore the design space of low power thermal reliable on-chip interconnect synthesis featuring nanophotonics Wavelength Div…
A High-Performance Triple Patterning Layout Decomposer with Balanced Density
Bei Yu, Yen-Hung Lin, Gerard Luk-Pat +3
Triple patterning lithography (TPL) has received more and more attentions from industry as one of the leading candidate for 14nm/11nm nodes. In this paper, we propose a high perfor…
Methodology for standard cell compliance and detailed placement for triple patterning lithography
Bei Yu, Xiaoqing Xu, Jhih-Rong Gao +1
As the feature size of semiconductor process further scales to sub-16nm technology node, triple patterning lithography (TPL) has been regarded one of the most promising lithography…