93 citations · 379 across the 19 of their papers we have counts for
14 papers · 1 filter
Lithography Hotspot Detection and Mitigation in Nanometer VLSI
Jhih-Rong Gao, Bei Yu, David Z. Pan
With continued feature size scaling, even state of the art semiconductor manufacturing processes will often run into layouts with poor printability and yield. Identifying lithograp…
TRIAD: a triple patterning lithography aware detailed router
Yen-Hung Lin, Bei Yu, David Z. Pan +1
TPL-friendly detailed routers require a systematic approach to detect TPL conflicts. However, the complexity of conflict graph (CG) impedes directly detecting TPL conflicts in CG.…
EPIC: Efficient prediction of IC manufacturing hotspots with a unified meta-classification formulation
Duo Ding, Bei Yu, Joydeep Ghosh +1
In this paper we present EPIC, an efficient and effective predictor for IC manufacturing hotspots in deep sub-wavelength lithography. EPIC proposes a unified framework to combine d…
GLOW: A global router for low-power thermal-reliable interconnect synthesis using photonic wavelength multiplexing
Duo Ding, Bei Yu, David Z. Pan
In this paper, we examine the integration potential and explore the design space of low power thermal reliable on-chip interconnect synthesis featuring nanophotonics Wavelength Div…
Multi-Voltage and Level-Shifter Assignment Driven Floorplanning
Bei Yu, Sheqin Dong, Statoshi Goto
As technology scales, low power design has become a significant requirement for SOC designers. Among the existing techniques, Multiple-Supply Voltage (MSV) is a popular and effecti…
A High-Performance Triple Patterning Layout Decomposer with Balanced Density
Bei Yu, Yen-Hung Lin, Gerard Luk-Pat +3
Triple patterning lithography (TPL) has received more and more attentions from industry as one of the leading candidate for 14nm/11nm nodes. In this paper, we propose a high perfor…
Methodology for standard cell compliance and detailed placement for triple patterning lithography
Bei Yu, Xiaoqing Xu, Jhih-Rong Gao +1
As the feature size of semiconductor process further scales to sub-16nm technology node, triple patterning lithography (TPL) has been regarded one of the most promising lithography…
Floorplanning and Topology Generation for Application-Specific Network-on-Chip
Bei Yu, Sheqin Dong, Song Chen +1
Network-on-chip (NoC) architectures have been proposed as a promising alternative to classical bus-based communication architectures. In this paper, we propose a two phases framewo…
Network flow-based simultaneous retiming and slack budgeting for low power design
Bei Yu, Sheqin Dong, Yuchun Ma +4
Low power design has become one of the most significant requirements when CMOS technology entered the nanometer era. Therefore, timing budget is often performed to slow down as man…
Layout decomposition for triple patterning lithography
Bei Yu, Kun Yuan, Boyang Zhang +2
As minimum feature size and pitch spacing further decrease, triple patterning lithography (TPL) is a possible 193nm extension along the paradigm of double patterning lithography (D…
Self-Aligned Double Patterning Friendly Configuration for Standard Cell Library Considering Placement
Jhih-Rong Gao, Bei Yu, Ru Huang +1
Self-aligned double patterning (SADP) has become a promising technique to push pattern resolution limit to sub-22nm technology node. Although SADP provides good overlay controllabi…
E-BLOW: E-Beam Lithography Overlapping aware Stencil Planning for MCC System
Bei Yu, Kun Yuan, Jhih-Rong Gao +1
Electron beam lithography (EBL) is a promising maskless solution for the technology beyond 14nm logic node. To overcome its throughput limitation, recently the traditional EBL syst…
Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting
Bei Yu, Jhih-Rong Gao, David Z. Pan
Triple patterning lithography (TPL) is one of the most promising techniques in the 14nm logic node and beyond. However, traditional LELELE type TPL technology suffers from native c…
L-Shape based Layout Fracturing for E-Beam Lithography
Bei Yu, Jhih-Rong Gao, David Z. Pan
Layout fracturing is a fundamental step in mask data preparation and e-beam lithography (EBL) writing. To increase EBL throughput, recently a new L-shape writing strategy is propos…