1 citations · 2 across the 5 of their papers we have counts for
5 papers
Timing Driven C-Slow Retiming on RTL for MultiCores on FPGAs
Tobias Strauch
In this paper C-Slow Retiming (CSR) on RTL is discussed. CSR multiplies the functionality of cores by adding the same number of registers into each path. The technique is ideal for…
Deriving AOC C-Models from D&V Languages for Single- or Multi-Threaded Execution Using C or C++
Tobias Strauch
The C language is getting more and more popular as a design and verification language (DVL). SystemC, ParC [1] and Cx [2] are based on C. C-models of the design and verification en…
A Novel RTL ATPG Model Based on Gate Inherent Faults (GIF-PO) of Complex Gates
Tobias Strauch
This paper starts with a comprehensive survey on RTL ATPG. It then proposes a novel RTL ATPG model based on "Gate Inherent Faults" (GIF). These GIF are extracted from each complex…
Using System Hyper Pipelining (SHP) to Improve the Performance of a Coarse-Grained Reconfigurable Architecture (CGRA) Mapped on an FPGA
Tobias Strauch
The well known method C-Slow Retiming (CSR) can be used to automatically convert a given CPU into a multithreaded CPU with independent threads. These CPUs are then called streaming…
Running Identical Threads in C-Slow Retiming based Designs for Functional Failure Detection
Tobias Strauch
This paper shows the usage of C-Slow Retiming (CSR) in safety critical and low power applications. CSR generates C copies of a design by reusing the given logic resources in a time…