3 papers
cs.AR2018
Timing Driven C-Slow Retiming on RTL for MultiCores on FPGAs
Tobias Strauch
In this paper C-Slow Retiming (CSR) on RTL is discussed. CSR multiplies the functionality of cores by adding the same number of registers into each path. The technique is ideal for…
cs.AR2018
Deriving AOC C-Models from D&V Languages for Single- or Multi-Threaded Execution Using C or C++
Tobias Strauch
The C language is getting more and more popular as a design and verification language (DVL). SystemC, ParC [1] and Cx [2] are based on C. C-models of the design and verification en…
cs.AR2015
Running Identical Threads in C-Slow Retiming based Designs for Functional Failure Detection
Tobias Strauch
This paper shows the usage of C-Slow Retiming (CSR) in safety critical and low power applications. CSR generates C copies of a design by reusing the given logic resources in a time…