6 citations · 8 across the 13 of their papers we have counts for
15 papers
Gradient Estimation Methods of Approximate Multipliers for High-Accuracy Retraining of Deep Learning Models
Chang Meng, Wayne Burleson, Giovanni De Micheli
Approximate multipliers (AppMults) are widely used in deep learning accelerators to reduce their area, delay, and power consumption. However, AppMults introduce arithmetic errors i…
Cut Tracing with E-Graphs for Boolean FHE Circuit Synthesis
Julien de Castelnau, Mingfei Yu, Giovanni De Micheli
Fully Homomorphic Encryption (FHE) is a promising privacy-preserving technology enabling secure computation over encrypted data. A major limitation of current FHE schemes is their…
Simulation-Guided Approximate Logic Synthesis Under the Maximum Error Constraint
Chang Meng, Weikang Qian, Giovanni De Micheli
Approximate computing is an effective computing paradigm for improving the energy efficiency of error-tolerant applications. Approximate logic synthesis (ALS) is an automatic proce…
Unleashing the Power of T1-cells in SFQ Arithmetic Circuits
Rassul Bairamkulov, Mingfei Yu, Giovanni De Micheli
Rapid single-flux quantum (RSFQ), a leading cryogenic superconductive electronics (SCE) technology, offers extremely low power dissipation and high speed. However, implementing RSF…
Towards Multiphase Clocking in Single-Flux Quantum Systems
Rassul Bairamkulov, Giovanni De Micheli
Rapid single-flux quantum (RSFQ) is one of the most advanced superconductive electronics technologies. SFQ systems operate at tens of gigahertz with up to three orders of magnitude…
AnySyn: A Cost-Generic Logic Synthesis Framework with Customizable Cost Functions
Hanyu Wang, Siang-Yun Lee, Giovanni De Micheli
Modern technology-independent logic synthesis has been developed to optimize for the size and depth of AND-Inverter Graphs (AIGs) as a proxy of CMOS circuit area and delay. However…
An Automated Testing and Debugging Toolkit for Gate-Level Logic Synthesis Applications
Siang-Yun Lee, Heinz Riener, Giovanni De Micheli
Correctness and robustness are essential for logic synthesis applications, but they are often only tested with a limited set of benchmarks. Moreover, when the application fails on…
Irredundant Buffer and Splitter Insertion and Scheduling-Based Optimization for AQFP Circuits
Siang-Yun Lee, Heinz Riener, Giovanni De Micheli
The adiabatic quantum-flux parametron (AQFP) is a promising energy-efficient superconducting technology. Before technology mapping, additional buffer and splitter cells need to be…
Simulation-Guided Boolean Resubstitution
Siang-Yun Lee, Heinz Riener, Alan Mishchenko +2
This paper proposes a new logic optimization paradigm based on circuit simulation, which reduces the need for Boolean computations such as SAT-solving or constructing BDDs. The pap…
ROS: Resource-constrained Oracle Synthesis for Quantum Computers
Giulia Meuli, Mathias Soeken, Martin Roetteler +1
We present a completely automatic synthesis framework for oracle functions, a central part in many quantum algorithms. The proposed framework for resource-constrained oracle synthe…
The Role of Multiplicative Complexity in Compiling Low T-count Oracle Circuits
Giulia Meuli, Mathias Soeken, Earl Campbell +2
We present a constructive method to create quantum circuits that implement oracles for -variabl…
Reversible Pebbling Game for Quantum Memory Management
Giulia Meuli, Mathias Soeken, Martin Roetteler +2
Quantum memory management is becoming a pressing problem, especially given the recent research effort to develop new and more complex quantum algorithms. The only existing automati…
Exact Synthesis of ESOP Forms
Heinz Riener, Rüdiger Ehlers, Bruno Schmitt +1
We present an exact synthesis approach for computing Exclusive-or Sum-of-Products (ESOP) forms with a minimum number of product terms using Boolean satisfiability. Our approach fin…
Developing Synthesis Flows Without Human Knowledge
Cunxi Yu, Houping Xiao, Giovanni De Micheli
Design flows are the explicit combinations of design transformations, primarily involved in synthesis, placement and routing processes, to accomplish the design of Integrated Circu…
FRAME: Fast and Realistic Attacker Modeling and Evaluation for Temporal Logical Correlation in Static Noise
Sungroh Yoon, Nahmsuk Oh, Peivand Tehrani +2
We propose a method called Fast and Realistic Attacker Modeling and Evaluation (FRAME) that can reduce pessimism in static noise analysis by exploiting temporal logical correlation…