2 papers
eess.SP2025
A 40 GHz Low-Power Variable-Gain Low Noise Amplifier in 28-nm CMOS Process
Harshith Reddy, Pankaj Arora
A Low-Power Variable Gain (VG) mm-Wave Low Noise Amplifier (LNA) is designed and simulated in a 28-nm CMOS process. The LNA utilizes a simple, yet novel, technique presented in thi…
eess.SY2025
A 16.28 ppm/C Temperature Coefficient, 0.5V Low-Voltage CMOS Voltage Reference with Curvature Compensation
Harshith Reddy, Pankaj Arora
This paper presents a fully-integrated CMOS voltage reference designed in a 90 nm process node using low voltage threshold (LVT) transistor models. The voltage reference leverages…