150 citations · 258 across the 16 of their papers we have counts for
4 papers · 1 filter
Adaptive-Latency DRAM (AL-DRAM)
Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko +4
This paper summarizes the idea of Adaptive-Latency DRAM (AL-DRAM), which was published in HPCA 2015. The key goal of AL-DRAM is to exploit the extra margin that is built into the D…
Achieving both High Energy Efficiency and High Performance in On-Chip Communication using Hierarchical Rings with Deflection Routing
Rachata Ausavarungnirun, Chris Fallin, Xiangyao Yu +5
Hierarchical ring networks, which hierarchically connect multiple levels of rings, have been proposed in the past to improve the scalability of ring interconnects, but past hierarc…
Enabling Efficient Dynamic Resizing of Large DRAM Caches via A Hardware Consistent Hashing Mechanism
Kevin K. Chang, Gabriel H. Loh, Mithuna Thottethodi +6
Die-stacked DRAM has been proposed for use as a large, high-bandwidth, last-level cache with hundreds or thousands of megabytes of capacity. Not all workloads (or phases) can produ…
Reducing Performance Impact of DRAM Refresh by Parallelizing Refreshes with Accesses
Kevin Kai-Wei Chang, Donghyuk Lee, Zeshan Chishti +4
Modern DRAM cells are periodically refreshed to prevent data loss due to leakage. Commodity DDR DRAM refreshes cells at the rank level. This degrades performance significantly beca…