9 citations · 29 across the 11 of their papers we have counts for
3 papers · 1 filter
Understanding and Exploiting Design-Induced Latency Variation in Modern DRAM Chips
Donghyuk Lee, Samira Khan, Lavanya Subramanian +5
Variation has been shown to exist across the cells within a modern DRAM chip. We empirically demonstrate a new form of variation that exists within a real DRAM chip, induced by the…
Enabling Efficient Dynamic Resizing of Large DRAM Caches via A Hardware Consistent Hashing Mechanism
Kevin K. Chang, Gabriel H. Loh, Mithuna Thottethodi +6
Die-stacked DRAM has been proposed for use as a large, high-bandwidth, last-level cache with hundreds or thousands of megabytes of capacity. Not all workloads (or phases) can produ…
Tiered-Latency DRAM (TL-DRAM)
Donghyuk Lee, Yoongu Kim, Vivek Seshadri +3
This paper summarizes the idea of Tiered-Latency DRAM, which was published in HPCA 2013. The key goal of TL-DRAM is to provide low DRAM latency at low cost, a critical problem in m…