activity
20152022
most citedSQUASH: Simple QoS-Aware High-Performance Memory Scheduler for Heterogeneous Systems with Hardware Accelerators

8 citations · 10 across the 4 of their papers we have counts for

collaborators

7 papers

cs.AR2022

FARSI: Facebook AR System Investigator for Agile Domain-Specific System-on-Chip Exploration

Behzad Boroujerdian, Ying Jing, Amit Kumar +7

Domain-specific SoCs (DSSoCs) are attractive solutions for domains with stringent power/performance/area constraints; however, they suffer from two fundamental complexities. On the…

cs.AR20202 cited

GenASM: A High-Performance, Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis

Damla Senol Cali, Gurpreet S. Kalsi, Zülal Bingöl +13

Genome sequence analysis has enabled significant advancements in medical and scientific areas such as personalized medicine, outbreak tracing, and the understanding of evolution. U…

cs.AR2018

Predictable Performance and Fairness Through Accurate Slowdown Estimation in Shared Main Memory Systems

Lavanya Subramanian, Vivek Seshadri, Yoongu Kim +2

This paper summarizes the ideas and key concepts in MISE (Memory Interference-induced Slowdown Estimation), which was published in HPCA 2013 [97], and examines the work's significa…

cs.AR2018

Tiered-Latency DRAM: Enabling Low-Latency Main Memory at Low Cost

Donghyuk Lee, Yoongu Kim, Vivek Seshadri +3

This paper summarizes the idea of Tiered-Latency DRAM (TL-DRAM), which was published in HPCA 2013, and examines the work's significance and future potential. The capacity and cost-…

cs.AR2018

High-Performance and Energy-Effcient Memory Scheduler Design for Heterogeneous Systems

Rachata Ausavarungnirun, Gabriel H. Loh, Lavanya Subramanian +2

When multiple processor cores (CPUs) and a GPU integrated together on the same chip share the off-chip DRAM, requests from the GPU can heavily interfere with requests from the CPUs…

cs.AR20158 cited

SQUASH: Simple QoS-Aware High-Performance Memory Scheduler for Heterogeneous Systems with Hardware Accelerators

Hiroyuki Usui, Lavanya Subramanian, Kevin Chang +1

Modern SoCs integrate multiple CPU cores and Hardware Accelerators (HWAs) that share the same main memory system, causing interference among memory requests from different agents.…