9 citations · 29 across the 11 of their papers we have counts for
11 papers
FARSI: Facebook AR System Investigator for Agile Domain-Specific System-on-Chip Exploration
Behzad Boroujerdian, Ying Jing, Amit Kumar +7
Domain-specific SoCs (DSSoCs) are attractive solutions for domains with stringent power/performance/area constraints; however, they suffer from two fundamental complexities. On the…
GenASM: A High-Performance, Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis
Damla Senol Cali, Gurpreet S. Kalsi, Zülal Bingöl +13
Genome sequence analysis has enabled significant advancements in medical and scientific areas such as personalized medicine, outbreak tracing, and the understanding of evolution. U…
Predictable Performance and Fairness Through Accurate Slowdown Estimation in Shared Main Memory Systems
Lavanya Subramanian, Vivek Seshadri, Yoongu Kim +2
This paper summarizes the ideas and key concepts in MISE (Memory Interference-induced Slowdown Estimation), which was published in HPCA 2013 [97], and examines the work's significa…
Tiered-Latency DRAM: Enabling Low-Latency Main Memory at Low Cost
Donghyuk Lee, Yoongu Kim, Vivek Seshadri +3
This paper summarizes the idea of Tiered-Latency DRAM (TL-DRAM), which was published in HPCA 2013, and examines the work's significance and future potential. The capacity and cost-…
High-Performance and Energy-Effcient Memory Scheduler Design for Heterogeneous Systems
Rachata Ausavarungnirun, Gabriel H. Loh, Lavanya Subramanian +2
When multiple processor cores (CPUs) and a GPU integrated together on the same chip share the off-chip DRAM, requests from the GPU can heavily interfere with requests from the CPUs…
Understanding and Exploiting Design-Induced Latency Variation in Modern DRAM Chips
Donghyuk Lee, Samira Khan, Lavanya Subramanian +5
Variation has been shown to exist across the cells within a modern DRAM chip. We empirically demonstrate a new form of variation that exists within a real DRAM chip, induced by the…
Enabling Efficient Dynamic Resizing of Large DRAM Caches via A Hardware Consistent Hashing Mechanism
Kevin K. Chang, Gabriel H. Loh, Mithuna Thottethodi +6
Die-stacked DRAM has been proposed for use as a large, high-bandwidth, last-level cache with hundreds or thousands of megabytes of capacity. Not all workloads (or phases) can produ…
Tiered-Latency DRAM (TL-DRAM)
Donghyuk Lee, Yoongu Kim, Vivek Seshadri +3
This paper summarizes the idea of Tiered-Latency DRAM, which was published in HPCA 2013. The key goal of TL-DRAM is to provide low DRAM latency at low cost, a critical problem in m…
Providing High and Controllable Performance in Multicore Systems Through Shared Resource Management
Lavanya Subramanian
Multiple applications executing concurrently on a multicore system interfere with each other at different shared resources such as main memory and shared caches. Such inter-applica…
SQUASH: Simple QoS-Aware High-Performance Memory Scheduler for Heterogeneous Systems with Hardware Accelerators
Hiroyuki Usui, Lavanya Subramanian, Kevin Chang +1
Modern SoCs integrate multiple CPU cores and Hardware Accelerators (HWAs) that share the same main memory system, causing interference among memory requests from different agents.…
The Blacklisting Memory Scheduler: Balancing Performance, Fairness and Complexity
Lavanya Subramanian, Donghyuk Lee, Vivek Seshadri +2
In a multicore system, applications running on different cores interfere at main memory. This inter-application interference degrades overall system performance and unfairly slows…