269 citations · 1.1k across the 57 of their papers we have counts for
16 papers · 1 filter
Enabling Efficient RDMA-based Synchronous Mirroring of Persistent Memory Transactions
Arash Tavakkol, Aasheesh Kolli, Stanko Novakovic +10
Synchronous Mirroring (SM) is a standard approach to building highly-available and fault-tolerant enterprise storage systems. SM ensures strong data consistency by maintaining mult…
What Your DRAM Power Models Are Not Telling You: Lessons from a Detailed Experimental Study
Saugata Ghose, Abdullah Giray Yağlıkçı, Raghav Gupta +9
Main memory (DRAM) consumes as much as half of the total system power in a computer today, resulting in a growing need to develop new DRAM architectures and systems that consume le…
Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation
Yixin Luo, Saugata Ghose, Yu Cai +2
Compared to planar (i.e., two-dimensional) NAND flash memory, 3D NAND flash memory uses a new flash cell design, and vertically stacks dozens of silicon layers in a single chip. Th…
Techniques for Efficiently Handling Power Surges in Fuel Cell Powered Data Centers: Modeling, Analysis, Results
Yang Li, Di Wang, Saugata Ghose +7
Fuel cells are a promising power source for future data centers, offering high energy efficiency, low greenhouse gas emissions, and high reliability. However, due to mechanical lim…
Characterizing, Exploiting, and Mitigating Vulnerabilities in MLC NAND Flash Memory Programming
Yu Cai, Saugata Ghose, Yixin Luo +3
This paper summarizes our work on experimentally analyzing, exploiting, and addressing vulnerabilities in multi-level cell NAND flash memory programming, which was published in the…
Read Disturb Errors in MLC NAND Flash Memory
Yu Cai, Yixin Luo, Saugata Ghose +3
This paper summarizes our work on experimentally characterizing, mitigating, and recovering read disturb errors in multi-level cell (MLC) NAND flash memory, which was published in…
SoftMC: Practical DRAM Characterization Using an FPGA-Based Infrastructure
Hasan Hassan, Nandita Vijaykumar, Samira Khan +6
This paper summarizes the SoftMC DRAM characterization infrastructure, which was published in HPCA 2017, and examines the work's significance and future potential. SoftMC (Soft Mem…
LISA: Increasing Internal Connectivity in DRAM for Fast Data Movement and Low Latency
Kevin K. Chang, Prashant J. Nair, Saugata Ghose +3
This paper summarizes the idea of Low-Cost Interlinked Subarrays (LISA), which was published in HPCA 2016, and examines the work's significance and future potential. Contemporary s…
Voltron: Understanding and Exploiting the Voltage-Latency-Reliability Trade-Offs in Modern DRAM Chips to Improve Energy Efficiency
Kevin K. Chang, Abdullah Giray Yaglıkçı, Saugata Ghose +7
This paper summarizes our work on experimental characterization and analysis of reduced-voltage operation in modern DRAM chips, which was published in SIGMETRICS 2017, and examines…
Flexible-Latency DRAM: Understanding and Exploiting Latency Variation in Modern DRAM Chips
Kevin K. Chang, Abhijith Kashyap, Hasan Hassan +7
This article summarizes key results of our work on experimental characterization and analysis of latency variation and latency-reliability trade-offs in modern DRAM chips, which wa…
Experimental Characterization, Optimization, and Recovery of Data Retention Errors in MLC NAND Flash Memory
Yu Cai, Yixin Luo, Erich F. Haratsch +3
This paper summarizes our work on experimentally characterizing, mitigating, and recovering data retention errors in multi-level cell (MLC) NAND flash memory, which was published i…
Decoupling GPU Programming Models from Resource Management for Enhanced Programming Ease, Portability, and Performance
Nandita Vijaykumar, Kevin Hsieh, Gennady Pekhimenko +6
The application resource specification--a static specification of several parameters such as the number of threads and the scratchpad memory usage per thread block--forms a critica…
Mosaic: An Application-Transparent Hardware-Software Cooperative Memory Manager for GPUs
Rachata Ausavarungnirun, Joshua Landgraf, Vance Miller +4
Modern GPUs face a trade-off on how the page size used for memory management affects address translation and demand paging. Support for multiple page sizes can help relax the page…
Holistic Management of the GPGPU Memory Hierarchy to Manage Warp-level Latency Tolerance
Rachata Ausavarungnirun, Saugata Ghose, Onur Kayıran +4
In a modern GPU architecture, all threads within a warp execute the same instruction in lockstep. For a memory instruction, this can lead to memory divergence: the memory requests…
Zorua: Enhancing Programming Ease, Portability, and Performance in GPUs by Decoupling Programming Models from Resource Management
Nandita Vijaykumar, Kevin Hsieh, Gennady Pekhimenko +5
The application resource specification--a static specification of several parameters such as the number of threads and the scratchpad memory usage per thread block--forms a critica…
Enabling the Adoption of Processing-in-Memory: Challenges, Mechanisms, Future Research Directions
Saugata Ghose, Kevin Hsieh, Amirali Boroumand +2
Poor DRAM technology scaling over the course of many years has caused DRAM-based main memory to increasingly become a larger system bottleneck. A major reason for the bottleneck is…