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researcher

J. Ross

7 papers hereh-index 7237 citations28 works total

Matching runs newest-first, so older work may not be attached to this profile yet.

author position
  • first author3
  • middle author1
  • last author3

Across the 7 of 7 papers where every author was matched, so the position is known.

fields
  • cs.DC7
same name
  • J. Ross — 31 papers, h 14
  • J. Ross — 20 papers, h 25
  • J. Ross — 15 papers, h 24
  • J. Ross — 15 papers, h 31
  • J. Ross — 10 papers, h 5
  • J. Ross — 8 papers, h 28

Either other researchers who publish under this name, or the same person where the external sources have not merged their records.

identity via Semantic Scholar / OpenAlex

activity
20152017
most citedAn OpenSHMEM Implementation for the Adapteva Epiphany Coprocessor

8 citations · 21 across the 5 of their papers we have counts for

collaborators
Showing 2016Show all

4 papers · 1 filter

cs.DC2016★ 7 cited

OpenCL + OpenSHMEM Hybrid Programming Model for the Adapteva Epiphany Architecture

David Richie, James Ross

There is interest in exploring hybrid OpenSHMEM + X programming models to extend the applicability of the OpenSHMEM interface to more hardware architectures. We present a hybrid Op…

cs.DC2016★ 8 cited

An OpenSHMEM Implementation for the Adapteva Epiphany Coprocessor

James Ross, David Richie

This paper reports the implementation and performance evaluation of the OpenSHMEM 1.3 specification for the Adapteva Epiphany architecture within the Parallella single-board comput…

cs.DC2016★ 5 cited

Advances in Run-Time Performance and Interoperability for the Adapteva Epiphany Coprocessor

David A. Richie, James A. Ross

The energy-efficient Adapteva Epiphany architecture exhibits massive many-core scalability in a physically compact 2D array of RISC cores with a fast network-on-chip (NoC). The arc…

cs.DC2016

Implementing OpenSHMEM for the Adapteva Epiphany RISC Array Processor

James A. Ross, David A. Richie

The energy-efficient Adapteva Epiphany architecture exhibits massive many-core scalability in a physically compact 2D array of RISC cores with a fast network-on-chip (NoC). With fu…

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