activity
20152017
most citedAn OpenSHMEM Implementation for the Adapteva Epiphany Coprocessor

8 citations · 21 across the 5 of their papers we have counts for

collaborators

7 papers

cs.DC2017

A Distributed Shared Memory Model and C++ Templated Meta-Programming Interface for the Epiphany RISC Array Processor

David Richie, James Ross, Jamie Infantolino

The Adapteva Epiphany many-core architecture comprises a scalable 2D mesh Network-on-Chip (NoC) of low-power RISC cores with minimal uncore functionality. Whereas such a processor…

cs.DC2017★ 1 cited

I CAN HAS SUPERCOMPUTER? A Novel Approach to Teaching Parallel and Distributed Computing Concepts Using a Meme-Based Programming Language

David Richie, James Ross

A novel approach is presented to teach the parallel and distributed computing concepts of synchronization and remote memory access. The single program multiple data (SPMD) partitio…

cs.DC2016★ 7 cited

OpenCL + OpenSHMEM Hybrid Programming Model for the Adapteva Epiphany Architecture

David Richie, James Ross

There is interest in exploring hybrid OpenSHMEM + X programming models to extend the applicability of the OpenSHMEM interface to more hardware architectures. We present a hybrid Op…

cs.DC2016★ 8 cited

An OpenSHMEM Implementation for the Adapteva Epiphany Coprocessor

James Ross, David Richie

This paper reports the implementation and performance evaluation of the OpenSHMEM 1.3 specification for the Adapteva Epiphany architecture within the Parallella single-board comput…

cs.DC2016★ 5 cited

Advances in Run-Time Performance and Interoperability for the Adapteva Epiphany Coprocessor

David A. Richie, James A. Ross

The energy-efficient Adapteva Epiphany architecture exhibits massive many-core scalability in a physically compact 2D array of RISC cores with a fast network-on-chip (NoC). The arc…

cs.DC2016

Implementing OpenSHMEM for the Adapteva Epiphany RISC Array Processor

James A. Ross, David A. Richie

The energy-efficient Adapteva Epiphany architecture exhibits massive many-core scalability in a physically compact 2D array of RISC cores with a fast network-on-chip (NoC). With fu…