collaborators

7 papers

physics.app-ph2026

ATSim3.5D: A Multiscale Thermal Simulator for 3.5D-IC Systems based on Nonlinear Multigrid Method

Qipan Wang, Tianxiang Zhu, Yibo Lin +2

To resolve the rising temperatures in 3.5D-ICs, a thermal-aware design flow becomes increasingly crucial, necessitating an accurate and efficient thermal simulation tool. However,…

eess.SY2025

LaMoSys3.5D: Enabling 3.5D-IC-Based Large Language Model Inference Serving Systems via Hardware/Software Co-Design

Qipan Wang, Zhe Zhang, Shuangchen Li +5

The success of large language models LLMs amplifies the need for highthroughput energyefficient inference at scale. 3DDRAMbased accelerators provide high memory bandwidth and there…

math.NA2025

ATMPlace: Analytical Thermo-Mechanical-Aware Placement Framework for 2.5D-IC

Qipan Wang, Tianxiang Zhu, Tianyu Jia +3

Rising demand in AI and automotive applications is accelerating 2.5D IC adoption, with multiple chiplets tightly placed to enable high-speed interconnects and heterogeneous integra…

cs.AR2025

A Systematic Approach for Multi-objective Double-side Clock Tree Synthesis

Xun Jiang, Haoran Lu, Yuxuan Zhao +8

As the scaling of semiconductor devices nears its limits, utilizing the back-side space of silicon has emerged as a new trend for future integrated circuits. With intense interest,…

cond-mat.mes-hall2025

Overlay-aware Variation Study of Flip FET and Benchmark with CFET

Wanyue Peng, Haoran Lu, Jingru Jiang +5

In this work, we carried out an overlay-aware variation study on Flip FET (FFET) considering the impact on RC parasitics induced by the lithography misalignment in backside process…

physics.app-ph2025

A Tale of Two Sides of Wafer: Physical Implementation and Block-Level PPA on Flip FET with Dual-sided Signals

Haoran Lu, Xun Jiang, Yanbang Chu +7

As the conventional scaling of logic devices comes to an end, functional wafer backside and 3D transistor stacking are consensus for next-generation logic technology, offering cons…