54 citations · 129 across the 27 of their papers we have counts for
21 papers · 1 filter
PuDHammer: Experimental Analysis of Read Disturbance Effects of Processing-using-DRAM in Real DRAM Chips
Ismail Emir Yuksel, Akash Sood, Ataberk Olgun +6
Processing-using-DRAM (PuD) is a promising paradigm for alleviating the data movement bottleneck using DRAM's massive internal parallelism and bandwidth to execute very wide operat…
MegIS: High-Performance, Energy-Efficient, and Low-Cost Metagenomic Analysis with In-Storage Processing
Nika Mansouri Ghiasi, Mohammad Sadrosadati, Harun Mustafa +9
Metagenomics has led to significant advances in many fields. Metagenomic analysis commonly involves the key tasks of determining the species present in a sample and their relative…
Constable: Improving Performance and Power Efficiency by Safely Eliminating Load Instruction Execution
Rahul Bera, Adithya Ranganathan, Joydeep Rakshit +8
Load instructions often limit instruction-level parallelism (ILP) in modern processors due to data and resource dependences they cause. Prior techniques like Load Value Prediction…
An Experimental Characterization of Combined RowHammer and RowPress Read Disturbance in Modern DRAM Chips
Haocong Luo, Ismail Emir Yüksel, Ataberk Olgun +3
DRAM read disturbance can break memory isolation, a fundamental property to ensure system robustness (i.e., reliability, security, safety). RowHammer and RowPress are two different…
AERO: Adaptive Erase Operation for Improving Lifetime and Performance of Modern NAND Flash-Based SSDs
Sungjun Cho, Beomjun Kim, Hyunuk Cho +4
This work investigates a new erase scheme in NAND flash memory to improve the lifetime and performance of modern solid-state drives (SSDs). In NAND flash memory, an erase operation…
PUMA: Efficient and Low-Cost Memory Allocation and Alignment Support for Processing-Using-Memory Architectures
Geraldo F. Oliveira, Emanuele G. Esposito, Juan Gómez-Luna +1
Processing-using-DRAM (PUD) architectures impose a restrictive data layout and alignment for their operands, where source and destination operands (i) must reside in the same DRAM…