2 citations · 2 across the 2 of their papers we have counts for
2 papers
cs.AR2015
A Novel Architecture of Area Efficient FFT Algorithm for FPGA Implementation
Atin Mukherjee, Amitabha Sinha, Debesh Choudhury
Fast Fourier transform (FFT) of large number of samples requires huge hardware resources of field programmable gate arrays (FPGA), which needs more area and power. In this paper, w…
cs.AR2012★ 2 cited
Design Of A Reconfigurable DSP Processor With Bit Efficient Residue Number System
Chaitali Biswas Dutta, Partha Garai, Amitabha Sinha
Residue Number System (RNS), which originates from the Chinese Remainder Theorem, offers a promising future in VLSI because of its carry-free operations in addition, subtraction an…