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20132023
most citedResource-Aware Just-in-Time OpenCL Compiler for Coarse-Grained FPGA Overlays

3 citations · 5 across the 3 of their papers we have counts for

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cs.OH2013

Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for Efficient Verification of Image Signal Processing IPs/SoCs

Abhishek Jain, Giuseppe Bonanno, Hima Gupta +1

In this paper,we present Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for efficient verification of Image Signal Processing IP'…