13 citations · 18 across the 5 of their papers we have counts for
6 papers
Entropy Maximization in Sparse Matrix by Vector Multiplication ()
Paolo D'Alberto, Abhishek Jain, Ismail Bustany +2
The peak performance of any SpMV depends primarily on the available memory bandwidth and its effective use. GPUs, ASICs, and new FPGAs have higher and higher bandwidth; however, fo…
Resource-Aware Just-in-Time OpenCL Compiler for Coarse-Grained FPGA Overlays
Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy
FPGA vendors have recently started focusing on OpenCL for FPGAs because of its ability to leverage the parallelism inherent to heterogeneous computing platforms. OpenCL allows prog…
An Area-Efficient FPGA Overlay using DSP Block based Time-multiplexed Functional Units
Xiangwei Li, Abhishek Jain, Douglas Maskell +1
Coarse grained overlay architectures improve FPGA design productivity by providing fast compilation and software-like programmability. Throughput oriented spatially configurable ov…
Early Development of UVM based Verification Environment of Image Signal Processing Designs using TLM Reference Model of RTL
Abhishek Jain, Dr. Hima Gupta, Sandeep Jana +1
With semiconductor industry trend of smaller the better, from an idea to a final product, more innovation on product portfolio and yet remaining competitive and profitable are few…
Accelerating SystemVerilog UVM Based VIP to Improve Methodology for Verification of Image Signal Processing Designs Using HW Emulator
Abhishek Jain, Piyush Kumar Gupta, Dr. Hima Gupta +1
In this paper we present the development of Acceleratable UVCs from standard UVCs in SystemVerilog and their usage in UVM based Verification Environment of Image Signal Processing…
Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for Efficient Verification of Image Signal Processing IPs/SoCs
Abhishek Jain, Giuseppe Bonanno, Hima Gupta +1
In this paper,we present Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for efficient verification of Image Signal Processing IP'…