3 citations · 3 across the 2 of their papers we have counts for
3 papers
Resource-Aware Just-in-Time OpenCL Compiler for Coarse-Grained FPGA Overlays
Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy
FPGA vendors have recently started focusing on OpenCL for FPGAs because of its ability to leverage the parallelism inherent to heterogeneous computing platforms. OpenCL allows prog…
An Area-Efficient FPGA Overlay using DSP Block based Time-multiplexed Functional Units
Xiangwei Li, Abhishek Jain, Douglas Maskell +1
Coarse grained overlay architectures improve FPGA design productivity by providing fast compilation and software-like programmability. Throughput oriented spatially configurable ov…
Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for Efficient Verification of Image Signal Processing IPs/SoCs
Abhishek Jain, Giuseppe Bonanno, Hima Gupta +1
In this paper,we present Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for efficient verification of Image Signal Processing IP'…