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cs.AI2025
Learning to Debug: LLM-Organized Knowledge Trees for Solving RTL Assertion Failures
Yunsheng Bai, Haoxing Ren
Debugging is the dominant cost in modern hardware verification, where assertion failures are among the most frequent and expensive to resolve. While Large Language Models (LLMs) sh…
cs.AI2025
AssertionForge: Enhancing Formal Verification Assertion Generation with Structured Representation of Specifications and RTL
Yunsheng Bai, Ghaith Bany Hamad, Syed Suhaib +1
Generating SystemVerilog Assertions (SVAs) from natural language specifications remains a major challenge in formal verification (FV) due to the inherent ambiguity and incompletene…