activity
20102014
most citedDoping-less Tunnel Field Effect Transistor: Design and Investigation

648 citations · 1.4k across the 18 of their papers we have counts for

collaborators
Showing 2010Show all

11 papers · 1 filter

cond-mat.mes-hall2010★ 24 cited

Nanoscale SOI-MOSFETs with Electrically Induced Source/Drain Extension: Novel attributes and Design considerations for Suppressed Short-channel Effects

Ali A. Orouji, M. Jagadesh Kumar

Design considerations for a below 100 nm channel length SOI MOSFET with electrically induced shallow source/drain junctions are presented. Our simulation results demonstrate that t…

cond-mat.mes-hall2010

Proposal and design of a new SiC-emitter lateral NPM Schottky collector bipolar transistor on SOI for VLSI applications

M. Jagadesh Kumar, D. V. Rao

A novel bipolar transistor structure, namely, a SiC emitter lateral NPM Schottky collector bipolar transistor (SCBT) with a silicon-on-insulator (SOI) substrate is explored using t…

cond-mat.mes-hall2010★ 11 cited

Estimation and Compensation of Process Induced Variations in Nanoscale Tunnel Field Effect Transistors (TFETs) for Improved Reliability

Sneh Saurabh, M. Jagadesh Kumar

Tunnel Field Effect Transistors (TFET) have extremely low leakage current, exhibit excellent subthreshold swing and are less susceptible to short channel effects. However, TFETs do…

cond-mat.mes-hall2010★ 147 cited

Impact of Strain on Drain Current and Threshold Voltage of Nanoscale Double Gate Tunnel Field Effect Transistor: Theoretical Investigation and Analysis

Sneh Saurabh, M. Jagadesh Kumar

Tunnel field effect transistor (TFET) devices are attractive as they show good scalability and have very low leakage current. However they suffer from low on-current and high thres…

cond-mat.mes-hall2010

Realizing Wide Bandgap P-SiC-emitter Lateral Heterojunction Bipolar Transistors with low collectoremitter offset voltage and high current gain - A novel proposal using numerical simulation

M. Jagadesh Kumar, C. Linga Reddy

We report a novel method to reduce the collector-emitter offset-voltage of the wide bandgap SiC-P-emitter lateral HBTs using a dual-bandgap emitter. In our approach, the collector-…

cond-mat.mtrl-sci2010

Silicon-On-Insulator Lateral Dual Sidewall Schottky (SOI-LDSS) Concept for Improved Rectifier Performance: A Two-Dimensional Simulation Study

M. Jagadesh Kumar, C. Linga Reddy

In this paper, we demonstrate that the performance of silicon Schottky rectifiers on SOI can be significantly improved using a Lateral Dual Sidewall Schottky (LDSS) concept. Our re…