Impact of Strain on Drain Current and Threshold Voltage of Nanoscale Double Gate Tunnel Field Effect Transistor: Theoretical Investigation and Analysis

Abstract

Tunnel field effect transistor (TFET) devices are attractive as they show good scalability and have very low leakage current. However they suffer from low on-current and high threshold voltage. In order to employ the TFET for circuit applications, these problems need to be tackled. In this paper, a novel lateral strained double-gate TFET (SDGTFET) is presented. Using device simulation, we show that the SDGTFET has a higher on-current, low leakage, low threshold voltage, excellent subthreshold slope, and good short channel effects and also meets important ITRS guidelines.

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• Impact of gate leakage considerations in tunnel field effect transistor design
• Estimation and Compensation of Process Induced Variations in Nanoscale Tunnel Field Effect Transistors (TFETs) for Improved Reliability
• Device Improvement and Circuit Performance Evaluation of complete SiGe Double Gate Tunnel FETs