9 citations · 10 across the 11 of their papers we have counts for
5 papers · 1 filter
A Multi-domain Magneto Tunnel Junction for Racetrack Nanowire Strips
Prayash Dutta, Albert Lee, Kang L. Wang +2
Domain-wall memory (DWM) has SRAM class access performance, low energy, high endurance, high density, and CMOS compatibility. Recently, shift reliability and processing-using-memor…
Pinning Fault Mode Modeling for DWM Shifting
Kawsher Roxy, Stephen Longofono, Sebastien Olliver +2
Extreme scaling for purposes of achieving higher density and lower energy continues to increase the probability of memory faults. For domain wall (DW) memories, misalignment faults…
XDWM: A 2D Domain Wall Memory
Arifa Hoque, Alex K. Jones, Sanjukta Bhanja
Domain-Wall Memory (DWM) structures typically bundle nanowires shifted together for parallel access. Ironically, this organization does not allow the natural shifting of DWM to rea…
PIRM: Processing In Racetrack Memories
Sebastien Ollivier, Stephen Longofono, Prayash Dutta +3
The growth in data needs of modern applications has created significant challenges for modern systems leading a "memory wall." Spintronic Domain Wall Memory (DWM), related to Spin-…
Hybrid CMOS-MQCA Logic Architectures using Multi-Layer Spintronic Devices
Jayita Das, Syed M. Alam, Srinath Rajaram +1
We present a novel hybrid CMOS-MQCA architecture using multi-layer Spintronic devices as computing elements. A feasibility study is presented with 22nm CMOS where new approaches fo…