9 citations · 10 across the 11 of their papers we have counts for
11 papers
Distributed Hierarchical Temporal Memory with Shared Associative Memory for Cross-Entity Preemptive Warning
Pavia Bera, Jennifer Adorno, Sanjukta Bhanja
Anomaly detection in multivariate time series remains a critical challenge in large-scale distributed systems, where related entities may exhibit transferable precursor behavior pr…
Controllable Domain Wall Memories with Magnetic Topological Insulator
Arifa Hoque, Sanjukta Bhanja
Domain wall memories have undergone several changes over the years for faster shift, read, and write operations; however, fundamental issues persist due to creating pinning sites t…
Enhancing Biologically Inspired Hierarchical Temporal Memory with Hardware-Accelerated Reflex Memory
Pavia Bera, Sabrina Hassan Moon, Jennifer Adorno +2
The rapid expansion of the Internet of Things (IoT) generates zettabytes of data that demand efficient unsupervised learning systems. Hierarchical Temporal Memory (HTM), a third-ge…
Quantification of Uncertainties in Probabilistic Deep Neural Network by Implementing Boosting of Variational Inference
Pavia Bera, Sanjukta Bhanja
Modern neural network architectures have achieved remarkable accuracies but remain highly dependent on their training data, often lacking interpretability in their learned mappings…
A Multi-domain Magneto Tunnel Junction for Racetrack Nanowire Strips
Prayash Dutta, Albert Lee, Kang L. Wang +2
Domain-wall memory (DWM) has SRAM class access performance, low energy, high endurance, high density, and CMOS compatibility. Recently, shift reliability and processing-using-memor…
Pinning Fault Mode Modeling for DWM Shifting
Kawsher Roxy, Stephen Longofono, Sebastien Olliver +2
Extreme scaling for purposes of achieving higher density and lower energy continues to increase the probability of memory faults. For domain wall (DW) memories, misalignment faults…
XDWM: A 2D Domain Wall Memory
Arifa Hoque, Alex K. Jones, Sanjukta Bhanja
Domain-Wall Memory (DWM) structures typically bundle nanowires shifted together for parallel access. Ironically, this organization does not allow the natural shifting of DWM to rea…
PIRM: Processing In Racetrack Memories
Sebastien Ollivier, Stephen Longofono, Prayash Dutta +3
The growth in data needs of modern applications has created significant challenges for modern systems leading a "memory wall." Spintronic Domain Wall Memory (DWM), related to Spin-…
Hybrid CMOS-MQCA Logic Architectures using Multi-Layer Spintronic Devices
Jayita Das, Syed M. Alam, Srinath Rajaram +1
We present a novel hybrid CMOS-MQCA architecture using multi-layer Spintronic devices as computing elements. A feasibility study is presented with 22nm CMOS where new approaches fo…
Defect Analysis of MCA Wires
Anita Kumari, Javier F. Pulecio, Sanjukta Bhanja
As devices continue to scale, imperfections in the fabrication process will have a more substantial impact on the reliability of a system. In Magnetic Cellular Automata (MCA) data…
Maximum Error Modeling for Fault-Tolerant Computation using Maximum a posteriori (MAP) Hypothesis
Karthikeyan Lingasubramanian, Syed M. Alam, Sanjukta Bhanja
The application of current generation computing machines in safety-centric applications like implantable biomedical chips and automobile safety has immensely increased the need for…