24 citations · 71 across the 14 of their papers we have counts for
Showing cs.ARShow all
2 papers · 1 filter
cs.AR2013
Architectural improvements and 28 nm FPGA implementation of the APEnet+ 3D Torus network for hybrid HPC systems
Roberto Ammendola, Andrea Biagioni, Ottorino Frezza +7
Modern Graphics Processing Units (GPUs) are now considered accelerators for general purpose computation. A tight interaction between the GPU and the interconnection network is the…
cs.AR2012★ 8 cited
The Distributed Network Processor: a novel off-chip and on-chip interconnection network architecture
Andrea Biagioni, Francesca Lo Cicero, Alessandro Lonardo +7
One of the most demanding challenges for the designers of parallel computing architectures is to deliver an efficient network infrastructure providing low latency, high bandwidth c…