7 papers
VeriInteresting: An Empirical Study of Model Prompt Interactions in Verilog Code Generation
Luca Collini, Andrew Hennesee, Patrick Yubeaton +2
Rapid advances in language models (LMs) have created new opportunities for automated code generation while complicating trade-offs between model characteristics and prompt design c…
MARVEL: Multi-Agent RTL Vulnerability Extraction using Large Language Models
Luca Collini, Baleegh Ahmad, Joey Ah-kiow +1
Hardware security verification is a challenging and time-consuming task. Design engineers may use formal verification, linting, and functional simulation tests, coupled with analys…
VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verification
Patrick Yubeaton, Andre Nakkab, Weihua Xiao +4
This paper introduces VeriThoughts, a novel dataset designed for reasoning-based Verilog code generation. We establish a new benchmark framework grounded in formal verification met…
ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction
Luca Collini, Jitendra Bhandari, Chiara Muscari Tomajoli +6
In the modern global Integrated Circuit (IC) supply chain, protecting intellectual property (IP) is a complex challenge, and balancing IP loss risk and added cost for theft counter…
C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap
Luca Collini, Siddharth Garg, Ramesh Karri
High-Level Synthesis (HLS) tools offer rapid hardware design from C code, but their compatibility is limited by code constructs. This paper investigates Large Language Models (LLMs…
Can Reasoning Models Reason about Hardware? An Agentic HLS Perspective
Luca Collini, Andrew Hennessee, Ramesh Karri +1
Recent Large Language Models (LLMs) such as OpenAI o3-mini and DeepSeek-R1 use enhanced reasoning through Chain-of-Thought (CoT). Their potential in hardware design, which relies o…