6 citations · 12 across the 3 of their papers we have counts for
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cs.AR2013★ 6 cited
Row-Based Dual Vdd Assignment, for a Level Converter Free CSA Design and Its Near-Threshold Operation
Dipankar Saha, Aanan Chatterjee, Sayan Chatterjee +1
Subthreshold circuit designs are very much popular for some of the ultra low power applications, where the minimum energy consumption is the primary concern. But, due to the weak d…
cs.AR2013★ 6 cited
A Low-Voltage, Low-Power 4-bit BCD Adder, designed using the Clock Gated Power Gating, and the DVT Scheme
Dipankar Saha, Subhramita Basak, Sagar Mukherjee +1
This paper proposes a Low-Power, Energy Efficient 4-bit Binary Coded Decimal (BCD) adder design where the conventional 4-bit BCD adder has been modified with the Clock Gated Power…