2 citations · 2 across the 1 of their papers we have counts for
2 papers
physics.ins-det2023★ 2 cited
An FPGA-based readout chip emulator for the CMS ETL detector upgrade
L. Zhang, C. Edwards, D. Gong +9
We present an FPGA-based readout chip emulator board for the CMS Endcap Timing Layer (ETL) detector upgrade. The emulator board uses an Intel Cyclone 10 GX FPGA to emulate the digi…
physics.ins-det2021
A radiation tolerant clock generator for the CMS Endcap Timing Layer readout chip
H. Sun, Q. Sun, S. Biereigel +14
We present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version…