An FPGA-based readout chip emulator for the CMS ETL detector upgrade

Abstract

We present an FPGA-based readout chip emulator board for the CMS Endcap Timing Layer (ETL) detector upgrade. The emulator board uses an Intel Cyclone 10 GX FPGA to emulate the digital functions of four Endcap Layer Readout Chips (ETROCs). Based on the actual ETROC design, the firmware is implemented and verified. The emulator board is being used for the ETROC digital design verification and system development.

arXiv comment8 pages, 4 figures

References in corpus (4)

• A Low-Power Time-to-Digital Converter for the CMS Endcap Timing Layer (ETL) Upgrade
• Characterization of the CMS Endcap Timing Layer readout chip prototype with charge injection
• In-pixel automatic threshold calibration for the CMS Endcap Timing Layer readout chip
• A radiation tolerant clock generator for the CMS Endcap Timing Layer readout chip