4 citations · 4 across the 3 of their papers we have counts for
4 papers
Verification of Compiler-to-Accelerator Mappings for Machine Learning Accelerators
Akash Gaonkar, Mike He, Yi Li +8
To meet the performance needs of modern machine learning (ML) applications, ML compiler frameworks support compiler-to-accelerator mappings that offload parts of application code t…
FPGA Technology Mapping Using Sketch-Guided Program Synthesis
Gus Henry Smith, Ben Kushigian, Vishal Canumalla +6
FPGA technology mapping is the process of implementing a hardware design expressed in high-level HDL (hardware design language) code using the low-level, architecture-specific prim…
Generate Compilers from Hardware Models!
Gus Henry Smith, Ben Kushigian, Vishal Canumalla +3
Compiler backends should be automatically generated from hardware design language (HDL) models of the hardware they target. Generating compiler components directly from HDL can pro…
Application-Level Validation of Accelerator Designs Using a Formal Software/Hardware Interface
Bo-Yuan Huang, Steven Lyubomirsky, Yi Li +10
Ideally, accelerator development should be as easy as software development. Several recent design languages/tools are working toward this goal, but actually testing early designs o…