2 papers
cs.SE2026
Reality Is the Final Verifier: On Two Key Gaps in Agentic Software Engineering
Alexander Krentsel, Shubham Agarwal, Mert Cemri +5
Software development follows an implementation-verification loop in which developers or agents iteratively revise an implementation until an evaluator, such as a test suite, accept…
cs.AR2023
32-Bit RISC-V CPU Core on Logisim
Siddesh D. Patil, Premraj V. Jadhav, Siddharth Sankhe
This project focuses on making a RISC-V CPU Core using the Logisim software. RISC-V is significant because it will allow smaller device manufacturers to build hardware without payi…