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3d ic design 1architectural simulation 1backside power delivery network 1cache modeling 1clock-signal co-optimization 1ir-drop reduction 1performance evaluation 1power modeling 1routing congestion 1signal integrity 1thermal-aware floorplanning 1

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cs.CE2026

CSCO: A Backside-PDN-Aware Clock-Signal Co-Optimization Framework for Improved PPA

Zixiao Wang, Leilei Jin, Zhen Zhuang +2

The paper presents CSCO, a data‑driven framework that jointly allocates limited backside power‑delivery network resources between clock and signal nets to improve power, performanc…