3d ic design 1architectural simulation 1backside power delivery network 1cache modeling 1clock-signal co-optimization 1ir-drop reduction 1performance evaluation 1power modeling 1routing congestion 1signal integrity 1thermal-aware floorplanning 1
From the 2 of 6 linked papers with an AI index.
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cs.AR2026
SynAct: A Reasoning-Acting Large Language Model Agent for Adaptive Synthesis Optimization
Fangzhou Liu, Peiyi Han, Jiawei Liu +5
Logic synthesis transforms RTL designs into gate-level netlists, where PPA results are highly sensitive to the choice of optimization commands, making synthesis tuning both high-di…
cs.AR2026
CLIP-3D: Closed-Loop Evaluation of Performance and Physical Constraints for 3D ICs
Shuo Ren, Libo Shen, Yaohui Han +6
The paper introduces CLIP-3D, a methodology that integrates power, cache, and thermal models with architectural simulation to evaluate the performance and physical constraints of 3…
cs.AR2026
Chiplet3D: Pin- and Thermal-Aware 3D Chiplet Floorplanning via Convolution-Embedded MILP
Shuo Ren, Libo Shen, Yaohui Han +4
As traditional Moore's Law scaling slows down, 3D-ICs stack multiple active dies vertically to sustain performance scaling. However, this vertical stacking traps heat inside, makin…