5 papers
SLED-IFV: Solver-Validated LLM-Guided Decomposition for Scalable Hardware Information-Flow Verification
Liangtao Dai, Yimin Gao, Melika Morsali +1
Formal hardware information-flow verification (IFV) provides strong guarantees against secret-dependent timing and control behavior, but often scales poorly on realistic RTL. We id…
High-Performance Low-Power Adiabatic Systolic Array Design in Advanced FinFET Nodes
Jun Yin, Liangtao Dai, Yimin Gao +1
Adiabatic logic has traditionally been recognized as a low-power solution but constrained to low clock speeds to preserve adiabatic behavior. For advanced FinFET nodes, however, cl…
Delayed Coupling Restores Ising Phase Dynamics in Physical Oscillator Networks
Yi Cheng, Liangtao Dai, Mircea R Stan +1
Oscillator-based Ising machines, in which the phases of coupled self-sustaining oscillators evolve toward decreasing an Ising Hamiltonian, are commonly interpreted as physical real…
Guarded Equivalence Predicates for Scalable Formal Hardware Information-Flow Verification
Liangtao Dai, Yimin Gao, Melika Morsali +1
Formal hardware information-flow verification is a principled way to rule out secret-dependent functional or timing observations, but scaling such proofs remains difficult. Self-co…
A Numerical-based Parametric Error Analysis Method for Goldschmidt Floating Point Division
Binzhe Yuan, Liangtao Dai, Xin Lou
This paper proposes a parametric error analysis method for Goldschmidt floating point division, which reveals how the errors of the intermediate results accumulate and propagate du…