5 citations · 5 across the 3 of their papers we have counts for
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cs.AR2023
Dynamic Ineffectuality-based Clustered Architectures
Rajshekar Kalayappan, Sandeep Chandran
The direction of conditional branches is predicted correctly in modern processors with great accuracy. We find several instructions in the dynamic instruction stream that contribut…
cs.AR2015★ 5 cited
Tejas Simulator : Validation against Hardware
Smruti R. Sarangi, Rajshekar Kalayappan, Prathmesh Kallurkar +1
In this report we show results that validate the Tejas architectural simulator against native hardware. We report mean error rates of 11.45% and 18.77% for the SPEC2006 and Splash2…