6 papers
Monte Cimone v3: Where RISC-V Stands in High-Performance Computing
Emanuele Venieri, Simone Manoni, Giacomo Madella +4
The Monte Cimone project provides a RISC-V testbed for High-Performacne Computing cluster. This paper presents Monte Cimone v3 (MCv3), the third iteration of the Monte Cimone RISC-…
AME-PIM: Can Memory be Your Next Tensor Accelerator?
Emanuele Venieri, Simone Manoni, Alberto Florian +3
High Bandwidth Memory with Processing-in-Memory (HBM-PIM) offers an opportunity to reduce data movement by executing computation directly inside memory, but current commercial plat…
CVA6-CFI: A First Glance at RISC-V Control-Flow Integrity Extensions
Simone Manoni, Emanuele Parisi, Riccardo Tedeschi +3
This work presents the first design, integration, and evaluation of the standard RISC-V extensions for Control-Flow Integrity (CFI). The Zicfiss and Zicfilp extensions aim at prote…
Monte Cimone v2: Down the Road of RISC-V High-Performance Computers
Emanuele Venieri, Simone Manoni, Gabriele Ceccolini +6
Many RISC-V (RV) platforms and SoCs have been announced in recent years targeting the HPC sector, but only a few of them are commercially available and engineered to fit the HPC re…
SpikeStream: Accelerating Spiking Neural Network Inference on RISC-V Clusters with Sparse Computation Extensions
Simone Manoni, Paul Scheffler, Luca Zanatta +3
Spiking Neural Network (SNN) inference has a clear potential for high energy efficiency as computation is triggered by events. However, the inherent sparsity of events poses challe…
Efficient Trace for RISC-V: Design, Evaluation, and Integration in CVA6
Umberto Laghi, Simone Manoni, Emanuele Parisi +1
In this work, we present the design and evaluation of a Processor Tracing System compliant with the RISC-V Efficient Trace specification for Instruction Branch Tracing. We integrat…