5 papers · 1 filter
CircuitGuard: Mitigating LLM Memorization in RTL Code Generation Against IP Leakage
Nowfel Mashnoor, Mohammad Akyash, Hadi Kamali +1
Large Language Models (LLMs) have achieved remarkable success in generative tasks, including register-transfer level (RTL) hardware synthesis. However, their tendency to memorize t…
TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization
Nowfel Mashnoor, Mohammad Akyash, Hadi Kamali +1
Achieving timing closure and design-specific optimizations in FPGA-targeted High-Level Synthesis (HLS) remains a significant challenge due to the complex interaction between archit…
LLM-IFT: LLM-Powered Information Flow Tracking for Secure Hardware
Nowfel Mashnoor, Mohammad Akyash, Hadi Kamali +1
As modern hardware designs grow in complexity and size, ensuring security across the confidentiality, integrity, and availability (CIA) triad becomes increasingly challenging. Info…
Self-HWDebug: Automation of LLM Self-Instructing for Hardware Security Verification
Mohammad Akyash, Hadi Mardani Kamali
The rise of instruction-tuned Large Language Models (LLMs) marks a significant advancement in artificial intelligence (AI) (tailored to respond to specific prompts). Despite their…
Evolutionary Large Language Models for Hardware Security: A Comparative Survey
Mohammad Akyash, Hadi Mardani Kamali
Automating hardware (HW) security vulnerability detection and mitigation during the design phase is imperative for two reasons: (i) It must be before chip fabrication, as post-fabr…