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20242026
most citedData is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework

59 citations · 61 across the 7 of their papers we have counts for

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cs.AI2025

ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning

Zhirong Chen, Kaiyan Chang, Zhuolin Li +8

Large Language Models have emerged as powerful tools for automating Register-Transfer Level (RTL) code generation, yet they face critical limitations: existing approaches typically…