10 citations · 15 across the 7 of their papers we have counts for
4 papers · 1 filter
Verifying Non-friendly Formal Verification Designs: Can We Start Earlier?
Bryan Olmos, Daniel Gerl, Aman Kumar +1
The design of Systems on Chips (SoCs) is becoming more and more complex due to technological advancements. Missed bugs can cause drastic failures in safety-critical environments le…
FuzzWiz -- Fuzzing Framework for Efficient Hardware Coverage
Deepak Narayan Gadde, Aman Kumar, Djones Lettnin +1
Ever-increasing design complexity of System-on-Chips (SoCs) led to significant verification challenges. Unlike software, bugs in hardware design are vigorous and eternal i.e., once…
Efficient Stimuli Generation using Reinforcement Learning in Design Verification
Deepak Narayan Gadde, Thomas Nalapat, Aman Kumar +3
The increasing design complexity of System-on-Chips (SoCs) has led to significant verification challenges, particularly in meeting coverage targets within a timely manner. At prese…
Improving Simulation Regression Efficiency using a Machine Learning-based Method in Design Verification
Deepak Narayan Gadde, Sebastian Simon, Djones Lettnin +1
The verification throughput is becoming a major challenge bottleneck, since the complexity and size of SoC designs are still ever increasing. Simply adding more CPU cores and runni…